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MSc Programmes in Engineering / 2000:015

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TITLE
A multi-chip architecture for high-capacity packet switching

AUTHOR
Wikander, Robert

DATE
2000-01-10

DEPARTMENT
Computer Science and Electrical Engineering / Computer Engineering

SUMMARY
It is the objective of this thesis to investigate a number of issues associated with building a scalable switch architecture to handle Ethernet and IP packet traffic.

When designing a multi-chip based solution a number of important design decisions have to be considered. Decisions regarding transmission techniques, control structure, signaling protocols, routing and redundancy issues. How to interconnect the multiple crossbar chips, i.e. how to configure the switching fabric, is also one of the fundamental issues.

We discuss the design issues and further analyze three of the more promising switching fabrics by simulations. It is concluded that, out of the three switching fabrics compared, the best performance is experienced by the Banyan switch.

We conclude the discussion by stating a number of guidelines for building a switching fabric which performs will, which we believe can help future designers when building multi-chip based switches for high-capacity packet switching.

ISSN 1402-1617 / ISRN LTU-EX--00/015--SE / NR 2000:015

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